In today's rapidly advancing semiconductor manufacturing industry, devices are being formed to include smaller device features and using more precise alignment tolerances. It is necessary to produce device features having desired sizes in all three dimensions. In order to produce device features having the desired and correct three dimensional size, it is necessary to control the thickness of the device features accurately. While this is true for all semiconductor device features, particular structures such as stacked MOM (metal oxide metal) capacitors and stacked RTMOM (rotated metal oxide metal) capacitors, are particularly sensitive to the thicknesses of the conductive layers used to form the stacked capacitors. While it is important to control the respective thicknesses of each of the individual metal layers used to form the MOM capacitors, it is equally important to control the aggregate thickness of the stacked layers used to form the MOM capacitors.
Methods are needed to control such parameters.